Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5
Oct 30, 2026. One of the most-discussed AI posts on Hacker News this week is an experiment called Qwenputer. Its author, Divyansh Agrawal, took a stock Qwen 3.5 4B model and compiled a working 32-bit RISC-V CPU directly into its weights, with no training involved. The CPU uses the model's own layers as RAM and runs inside ordinary forward passes, with no external tool, sandbox or Python runtime. Here's what that means, based on the author's write-up.
Primary source: https://divagr.com/blog/qwenputer (posted Oct. 22, 2026). Code: https://github.com/divagr18/qwenputer
The trick: using the model's RNN layers as memory
Qwen 3.5 is a hybrid model. According to the post, three of every four attention layers use Gated DeltaNet (GDN), a linear RNN where each head keeps a state matrix. Normally that state slowly "forgets" as new tokens arrive.
Agrawal found that if you fix the gate at 1 (nothing fades), set the write strength to 1 (old values are fully replaced) and use one-hot keys (each key points at exactly one row), every write overwrites exactly one row and every read returns an exact value. In other words, the GDN state behaves like addressable RAM. Because a GDN head's state stays the same size however long the conversation runs, he says this is far cheaper than using normal attention's KV cache as memory.
The post credits earlier work: Schlag, Irie and Schmidhuber (ICML 2021) showed delta-rule linear attention acts as associative memory. What's new, he says, is making it exact and reliable enough to run a whole CPU inside a production model.
Compiling a CPU into layers
No training is involved. A compiler sets every weight directly. The CPU is described as a circuit of small steps ("read this register", "add", "jump if zero"), and each step becomes part of a transformer layer: attention heads for lookups, feed-forward units for arithmetic and DeltaNet heads for RAM. Each instruction shows up as a few generated tokens (an address, a value and a STEP marker), so the CPU is literally running while the model generates them.
According to the post, the CPU is:
- a 32-bit RV32IM core plus the Zba extension and a small bignum unit;
- 11 extra layers in front of Qwen's 32;
- passing the official riscv-tests, matching qemu, and running 18 million instructions free-running without an error (author's figures);
- able to run C and MicroPython, slowly.
Qwen's original weights stay unchanged. The computer is added in extra dimensions and layers.
How Qwen uses it
Qwen calls the CPU through the tool-call format it already knows, but nothing leaves the model: the compiled layers run and write the "tool response" themselves. A small driver called RvChat loads firmware into the GDN state and keeps the trace tokens out of Qwen's own layers.
Does it work?
The author reports these results (self-reported, not independently verified):
- DeepMind arithmetic sets: div_big 97.5% (base Qwen 72.5%, Qwen with a Python tool 95%); mul_big 97.5% (base 55%, Python tool 100%).
- NUPA long-integer arithmetic: 48.6% to 100%, matching the Python tool.
- About 230,000 output positions replayed against a reference machine with zero mismatches.
- Normal text output within noise of base Qwen.
There's also an experimental in-model filesystem (up to 512 files, about 53,000 tokens) on a separate branch.
Limits
The author lists them plainly: the checkpoint is 18.8 GB, about double base Qwen (mostly zero padding). It needs RvChat, so a plain generate() call doesn't work yet. And it's slow: every instruction costs several decoded tokens, about 3,200 CPU tokens a second on an L4 with his batched executor. He says it runs on a single 24 GB GPU.
Why it matters
Beyond the novelty, the author pitches exact control of RNN state as a testbed for AI safety research, including follow-up posts on how hybrid models could hide reasoning in RNN state and how compiled weights could act as monitors a model can't switch off.
What's confirmed / not confirmed
Confirmed (author's blog post and GitHub link, read Oct. 30): architecture, the 11-layer RV32IM CPU, the RvChat requirement, the 18.8 GB size and the open code and model links are as described by the author.
Not confirmed: all accuracy and reliability numbers are the author's own and have not been independently reproduced. The license and download counts were not checked this run. The Qwen team has not commented, and this is not an Alibaba/Qwen release.
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